DFT Approaches Enable Mass Production Test

Test compression technology was adopted to enable additional scan patterns to be applied without changing the test interface. However, test compression and test approaches can also be used to reduce the ATE (automatic test equipment) and tester interface requirements. As a result, not only can existing testers be used to apply additional tests, the test interface can be reduced to a very small amount of serial channels. This eases the adoption of multi-site testing, thereby increasing test throughput and mass volume production. In addition, the compressed fail values of each device can be directly used for diagnostics, enabling a software approach to failure and yield analysis. Three industry designs are used to demonstrate high levels of compression with one or two serial channels. Results are shown in terms of improved test quality, test compression, and diagnostics while reducing the test interface for a mass production environment. Battling Increasing Test Requirements Whilst the economics of production test push for more tester throughput, quality goals are demanding more tests. Scan test is a standard methodology for almost all large digital devices with volume production. Automatic test pattern generation (ATPG) is facilitated by scan technology for even the most complex devices. With scan, every sequential gate is serially connected as a series of shift registers during test mode referred to as scan chains. As a result, each pattern serially loads the scan chains to place the entire circuit in a desired state. Next, the circuit is clocked and the functional response is captured. Finally, the circuit is again placed into shift mode to shift out the response for comparison. Moore’s law predicts that gate counts increase by roughly four times every three years [1]. Growth in gate count will increase the cycles and data per test pattern to at least the same rate. Thus, test time increases by a minimum of four times every three years since each scan chain grows four times longer. The same advances in silicon fabrication that enable increased gate counts also cause a change in the nature of defects that occur. As a result, the basic scan patterns that were sufficient for many companies five years ago need to be supplemented with other scan patterns. For example, devices produced with 130 nm or smaller fabrication processes often have a population of timing defects greater than 2%. Consequently, at-speed transition scan testing is mandatory in many production test environments. Additional tests are growing in popularity to further improve test quality and reduce defective parts from being shipped. Several example of the newer scan test methods are multiple-detect [2], timing-aware [3], open, and deterministic bridge patterns. Growing device gate counts and at-speed transition patterns can increase the device test time by a huge amount. This pattern growth is necessary just to maintain defects per million (DPM) levels as companies move to smaller technology nodes. Furthermore, any additional newer scan tests used to improve test quality or to deal with defects in new fabrication processes will grow the test time even more. Applying these tests can quickly exceed tester capacity if a solution isn’t found. Fortunately, compression technologies have been introduced to reduce the time and data to apply scan test patterns by as much as 100 times [4]. As a result, the additional tests can be applied without negatively impacting tester throughput. Figure 1. EDT (embedded deterministic test) applies tests 100x faster using the same tester scan channels Compressed